Low Power Modeling Of Topologically Compressed Static Flip- Flop

The increasing market trends of extremely low power operated handy applications like laptop, electronics gadgets etc requires microelectronic devices with low power consumption. It is obvious that the transistor dimensions continues to shrink and as require for more complex chips increases, power management of such deep sub-micron based chip is one of the major challenges in VLSI industry. The manufacturers are always targeting for low power designs for the reason that to provide adequate physical resources to withstand against design hurdles and this lead to increases the cost and restrict the functionality of the device. This power reduction ratio is the highest among FFs that have been reported so far. The reduction is achieved by applying topological compression technique, merger of logically equivalent transistors to an eccentric latch structure. Fewer transistors, only three, connected to clock signal which reduces the power drastically, and the smaller total transistor count assures to retain the chip area as conventional FFs. In addition, fully static full-swing operation makes the cell lenient of supply voltage and input slew variation. An experimental chip design with 32 nm CMOS technology shows that almost all conventional FFs are expendable with proposed FF while preserving the same system performance and layout area. The performance of this paper is evaluated on the design simulation using Microwind 3.1 simulator Index Terms — Low power systems, Flip-Flops, Topological Compression, Supply Voltage, 32 nm CMOS Technology.